GaN complementary metal–oxide–semiconductor (CMOS) technology on GaN-on-Si

Nadim Chowdhury

Electrical Engineering & Computer Science (EECS)
Microsystems Technology Laboratories (MTL)

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Thesis Committee
Tomas Palacios, Professor, EECS (Thesis supervisor)
Akintunde Akinwande, Thomas and Gerd Perkins Professor, EECS
Han Wui Then, Principal Engineer, Intel Corporation
Jesús Grajal de la Fuente, Professor, Universidad Politécnica de Madrid​

GaN, a wide band gap semiconductor, has some remarkable attributes like spontaneous and piezoelectric polarization charge, high electron mobility, and high saturation velocity which are useful for electronics. These properties enable n-channel GaN-based transistors to operate at  a higher switching speed, and at a higher power density than its Si counterpart.

To realize the full potential of GaN, the need for a complementary circuit technology cannot be overemphasized. A high performance GaN-CMOS technology could potentially find applications in data centers, electric vehicles, space electronics, on-chip power converters, beyond 5G base stations, and a plethora of other applications where Si falls short in terms of performance and efficiency. However, a major roadblock towards realizing such a technology is the lack of high-performance GaN p-channel transistors that can be monolithically integrated with GaN n-channel devices.

This thesis shows clear pathways to improve the current density of GaN p-channel transistors by demonstrating a self-aligned gate and a FinFET technology for the p-channel device. Our demonstrated GaN p-channel devices exhibit record performance in terms of on-current density, on-off ratio, subthreshold swing and on-resistance. This thesis for the first time demonstrates a GaN-CMOS technology on a 6-inch GaN-on-Si wafer by fabricating a monolithically integrated p-channel GaN transistor with an E-mode GaN n-channel device.