Duane Boning, Professor, EECS (Thesis supervisor)
Lionel Kimerling, Professor, Materials Science & Engineering
Jelena Notaros, Assistant Professor, EECS
The rapidly growing field of silicon photonics is an attractive research and manufacturing platform due to its ability to enable novel functionalities. Silicon photonics leverages existing CMOS processes and fabrication infrastructure, making its components suffer from the process variations present in CMOS technology. These process variations affect the behavior of components such that long and repetitive simulations are required to understand the effect of these variations, largely due to the lack variation-aware models.
This thesis explores methodologies for the development and application of process variation-aware compact models for silicon photonics components to enable photonics design for manufacturability. We consider the effect of a number of common unavoidable process variations, including both systematic and random variations, on the behavior of key optical building blocks. We examine the effect of line edge roughness as a random process variation on different components including, Y-branches and coupled resonator optical waveguides.
For the Y-branch, we use ensemble simulations to develop behavioral statistical models that can predict the behavior in the presence of different line edge roughness parameters. In the case of coupled resonator optical waveguides, to predict the behavior in the presence of different line edge roughness parameters, we develop an S-parameter based model that can be used directly in circuit simulation. Also, we present methods to develop S-parameter based compact models against systematic variations (geometric variations) in rings for both silicon and silicon nitride waveguides.
The models are capable of predicting the behavior much faster than by full wave simulations, and give insight on the performance variation to enable yield prediction and optimization. We present methods for extraction of spatial variations using variation test chip design and measurement. The spatial variations are decomposed into die-to-die and within-die variations. We use the developed compact model to simulate photonic integrated circuits and compare the time required with the case of traditional simulations loops.
We examine modulation (electrical and thermal) as a conventional approach to account for the effect of process variations. For electrical modulation, we study typical operation variations it can experience and find that their effect is not as severe as typical process variations. Moreover, the power budget required to correct for process variations is calculated.
Together, these methods are key components toward design-for-manufacturability approaches and serve as a basis for extended PDK for silicon photonics. Such models and methods help increase the speed of the simulation process required in photonics integrated circuit design, and inform designers of potential design modifications to correct for process variations for high yield and performance.