Tokyo Electron Day at MIT

Introduction: Tokyo Electron – TTCA

Tokyo Electron (TEL) is a Japanese tool manufacturer that specializes in high quality, ultra-clean tools for the semiconductor industry and is currently the #2 tool maker in the world with 65000 tools running worldwide. TEL Technology Center of America (TTCA) is the US R&D center located in Albany at the Nanotech campus which is home to many leading semiconductor manufacturing companies and cutting edge technology. Our mission is to develop innovative technology that can differentiate TEL products. TTCA is currently the largest RnD presence for Tokyo Electron outside of Japan and the only cross functional site the focuses on device enablement and pathfinding across all business units.

The Semiconductor Microchip Business and a Technology Enabler of the Information Age

This talk will introduce the semiconductor industry/roadmap, photolithography, and scaling techniques. To produce integrated circuits for everyday electronics, the semiconductor manufacturing relies on photolithography which is the process of transferring a pattern from a mask to a substrate using light. In order to increase the speed of computer chips, the transistor density is increased by reducing the size of the features. Moore’s law is the observation that the number of transistors on the integrated circuit (IC) chip doubles approximately every two years in order keep up with the technological demand. Traditionally, the feature size has been reduced through advancing lithography by improving the resolution and decreasing the imaging wavelength. However, engineers are facing roadblocks, such as source power and shot noise, with the next generation of lithography known as extreme ultra-violet radiation (EUV). So, in order to continue scaling while the challenges of EUV are being solved, patterning engineers must find alternative methods to continue advancing device performance. 

Traditional 2D Architecture and Scaling

Here, we will discuss traditional 2D scaling - the challenges and the solutions. Planar FET, finFET, and gate-all-around (GAA) are a few of the types of 2D designs that will be discussed. We will show both the conceptual modelling and the corresponding experimental data for some of these architectures highlighting the different technologies that were needed to implement the concepts (Atomic layer deposition, spacer transform, pattern splitting, and multi patterning technology).

Where does the cutoff of 2D architecture end and the pickup of 3D start? Modern chip designs have produced a plethora of options which gradually introduce high aspect ratio features that start reaching to greater degrees of 2D scaling. Lines blur as we strive to find the last capabilities in chip design until we inevitably go 3D. Some of these advance 2D, high aspect ratio scaling options will be explored such as buried power rail (BPR) and self-aligned gate contact (SAGC).

3D Integration – Searching for value beyond Moore, Dennard, and von Neumann

The semiconductor industry is on the verge of hitting what appears to be the most decisive scaling barrier yet. While the end of VLSI logic scaling has been prophesized and proven wrong many times in the last five decades, the pending end to any possibility of further reduction in critical dimensions is cause for concern. As with the many scaling barriers that have come before, we will engineer our way through this to prosper for many more technology nodes. Though unlike the barriers of the past, this one will require unprecedented interdisciplinary collaboration to maintain meaningful value-add at a time when the three main pillars that have supported this industry: Moore, Dennard, and von Neumann are all crumbling. 3D integration for logic scaling, unlike memory, is not merely an exercise in integrating transistor density in volume rather than area, it is an exercise in deriving value from highly-complex system-level benefits. Initially pitch-based scaling with a focus on resolution enhancement techniques (RET) gave way to design-technology co-optimization (DTCO) with a focus on scaling boosters such as self-aligned gate contacts (SAGC) and buried power-rails (BPR). Now we are transitioning to the era of system-technology co-optimization (STCO) to exploit value from solutions such as complementary FET (CFET) and 3D integrated logic. When once it was seen as revolutionary that etch engineers and lithography engineers collaborated, we are now challenged to synergistically innovate across the entire spectrum of the design-to-silicon infrastructure. After briefly reviewing the history of semiconductor scaling thus far, this talk will show examples of how engineers with skillsets in diametrically opposed specialties within our broad technical endeavor have to join forces to seek out opportunities for incremental value gain.

Etch Challenges at Current and Future Logic Nodes

As logic nodes continue to scale below 7nm, the back-end-of-line (BEOL) critical pitch has moved to sub-40 nm and is forecasted to scale down to 14 nm according to the latest IRDS published road map for logic.  In addition to the patterning complexities that arise with scaling to smaller size, pitch scaling has a direct impact on the plasma-processing window for plasma etching. As critical pitch decreases node to node, feature size dependent etch depth (RIE lag/ ARDE), mask selectivity, and plasma damage have become major issues that need to be addressed to meet required device performance. 

 RIE lag leads to wider trenches having a faster etch rate compared to narrower trenches, resulting in severe profile variations across features of varying sizes. Mask selectivity loss leads to degradation of line edge roughness, line width roughness, which can negatively affect electrical and reliability performance of a device. This is especially critical in extreme ultraviolet lithography (EUV) defined patterns where resist height is significantly lower than in conventional 193 immersion lithography. Tradeoffs in process optimization for mask selectivity and RIE lag must be balanced to reach the desired feature profile (taper angle, undercut, bowing, dimensions).  The etch tradeoff triangle in the figure below exemplifies the difficulty encountered when trying to optimize a process for a typical etch pattern transfer with EUV lithography.  In this talk, we will discuss the origins of these challenges and tradeoffs and present novel technologies developed to address them.

Materials and Tool Capabilities for 200mm / 8 in

TEL has a diverse fleet of tools at the 200 mm / 8” for R&D and manufacturing ranging in application from coaters/developers to plasma etchers. In this talk, we will show you a few of the most relevant tools, explain what differentiates them from other tools on the market, and discuss the science behind the process. To generate devices, or even simple test structures, one needs the ability to create a pattern on the substrate which requires film deposition and exposure tools and then transfer that pattern into the substrate through a series of either wet or dry etches. Usually, a process flow starts with deposition a stack of films. A thermal processing system, such as the Alpha 8SE, provides a wide range of process applications such as Wet/Dry Oxidation, Anneal, LPCVD of Si, Si3N4 and SiO2, and high-k ALD. Often after steps such as implantation or deposition, an anneal is required to relieve stress. TEL manufactures a magnetic field annealer with fields up to 0.2 Tesla and temperatures up to 400 degree C.  Then on top of the stack in order to create a pattern, a set of lithographic films are coated via a track. TEL specializes in the production of ultra-clean, high reliability coater/developer tracks such as the ACT 8 and the Lithius which allow the user to coat, bake, and develop films in a controlled and repeatable way. After the pattern is created, it needs to be transferred into the stack below which can be done using a RIE (reaction ion etch) on a plasma etcher, such as the Unity, which works with a variety of dielectric films. After successful transfer, the remaining sacrificial pattern is often removed by wet etch. The Zeta 200 or Semi Auto equipped with ViPR™ technology offers the highest performance and lowest cost for resist, silicide and general film stripping needs. After many layers, the topography at the surface becomes rough, which can be modulated with a corrective etch process available on the UltraTrimmer which can handle variety of wafer sizes seamlessly without any hardware changes. Now, a device is taking shape.

Quasar Direct Write Technology:  Lithography for the Digital Age

Optical lithography employs electromagnetic radiation to create high resolution relief image patterns in a photosensitive material (resist), which may then be effectively employed as a template for selective deposition and etch processes in a layered fabrication scheme.  The images realized in resist are typically projections of a master pattern on a photomask constructed of chromium and quartz which integrate to create opaque/transparent regions that dictate the propagation of source radiation at the mask interface.  This fundamental patterning process is used to generate the majority of electronic devices from those used in microwaves to cell phones, even NASA’s Curiosity Rover is comprised of components fabricated using projection lithography!

The time has come to transition this analog process to the digital domain and no longer be bound by mask fabrication lead time, cost and finality.  The TEL Quasar platform empowers the next generation of products and systems through its unique i-line digital light projection (DLP) mask-less lithography technology, circumventing traditional mask based patterning overhead with a direct write system where physical mask media are replaced by digital design files.  From computer to wafer, unconstrained micro-scale patterning has arrived. This talk introduces one of the world’s most adaptable, high-throughput fabrication tools; empowering academia, researchers, designers and integrators by reducing turn time and increasing cycles of learning.  Differentiate.  Explore.  Innovate.  TEL Quasar: lithography for the digital age.

Q&A Session

Final Remarks